Cannot Creat HDL wrapper successfully, there is an error: [BD 41-758] The following clock pins are not connected to a valid clock source: /processing_system7_0/M_AXI_GP0_ACLK

[AllenChenChao]

I fonud it failed to Creat HDL wrapper betwwen generate .bit file. I don’t know why, has anyone meet this problem before or know how to deal with it?

How to use axi interface created by HLS correctly?

Hello, I want to use axi interface in PYNQ.So I created an axi master IP with HLS examle project. I use that IP on vivado, and I find I can’t Creat HDL wrapper, there is an error: [BD 41-758] The following clock pins are not connected to a valid clock source: /processing_system7_0/M_AXI_GP0_ACLK I don’t how to deal with it. I choose or not choose HP0 or GP0, It does’t work. Is anyone know how to deal with it? I want to test it n PYNQ, hope it could be successfully. [vivado_kHFT7twXZP]