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How to use PYNQ CDMA?
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1
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426
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January 4, 2023
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Tutorial: AXI Master interfaces with HLS IP
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5
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5205
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January 4, 2023
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Docker, Xilinx Platforms & PYNQ
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7
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3871
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November 17, 2022
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PYNQ 3.0.1 VirtualBox install and SD build
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0
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988
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October 29, 2022
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Tutorial: Rebuilding the PYNQ base overlay (PYNQ v2.6)
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11
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7889
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October 14, 2022
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100 Gigabit Ethernet for RFSoC-PYNQ Overlays
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4
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4359
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October 4, 2022
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USB3320 not able to detect the devicec connected
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5
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546
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September 26, 2022
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Tutorial: Creating a new Verilog Module Overlay
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2
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4451
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August 25, 2022
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Starting PYNQ Programs At Boot
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7
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3821
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August 10, 2022
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GPS on PYNQ
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0
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301
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July 5, 2022
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Are PYNQ concept worth to move onto general FPGA with softcore CPU apart from SOC-based FPGA?
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0
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379
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July 4, 2022
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ZYNQ Ultrascale+ FIR DMA
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0
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549
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July 1, 2022
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Readability in Python and Java
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3
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258
|
June 30, 2022
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MNIST + AXI Stream on PYNQ 2.7 (Attention to Details)
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2
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1565
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June 6, 2022
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Servo motor on PYNQ
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0
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363
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May 24, 2022
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Using PyPI to deliver FPGA Overlays
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1
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2154
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March 15, 2022
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Testing PyTorch 1.8 in Zybo-Z7 running Pynq 2.7
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0
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995
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May 10, 2022
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Pynq - Z2 Pmod
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2
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376
|
May 6, 2022
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Kubernetes for AMD-Xilinx Platforms
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0
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934
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May 2, 2022
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Bluetooth on FPGA with ESP32
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0
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537
|
April 26, 2022
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FPGA as USB Device
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0
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489
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April 12, 2022
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Double tap with accelerometer
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0
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297
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March 1, 2022
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Interactive C++ on the Kria-SoM in Jupyter Lab
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2
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1904
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February 21, 2022
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Tutorial PYNQ: microblaze
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0
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737
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February 1, 2022
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Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)
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1
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8946
|
February 4, 2022
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Pynq 2.6 custom board image build method that works
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4
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3852
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January 21, 2022
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Cloning a git repository into your board connected to computer
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1
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860
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December 13, 2021
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Developing Verilog AXI Stream Overlays and interfacing to ZYNQ
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13
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3543
|
December 7, 2021
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My learning path with Pynq and Zynq
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0
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568
|
November 19, 2021
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Tutorial: use Axi Timer as an IP (no microblaze)
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0
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580
|
November 16, 2021
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