GPS on PYNQ
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|
0
|
172
|
July 5, 2022
|
Are PYNQ concept worth to move onto general FPGA with softcore CPU apart from SOC-based FPGA?
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0
|
215
|
July 4, 2022
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ZYNQ Ultrascale+ FIR DMA
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|
0
|
299
|
July 1, 2022
|
Readability in Python and Java
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3
|
166
|
June 30, 2022
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Testing Tensorflow 2.5 in Zybo-Z7 running Pynq 2.7
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6
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987
|
June 15, 2022
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MNIST + AXI Stream on PYNQ 2.7 (Attention to Details)
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2
|
1017
|
June 6, 2022
|
Servo motor on PYNQ
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0
|
227
|
May 24, 2022
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Using PyPI to deliver FPGA Overlays
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|
1
|
1875
|
March 15, 2022
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Testing PyTorch 1.8 in Zybo-Z7 running Pynq 2.7
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0
|
620
|
May 10, 2022
|
Pynq - Z2 Pmod
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2
|
246
|
May 6, 2022
|
Kubernetes for AMD-Xilinx Platforms
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0
|
747
|
May 2, 2022
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Bluetooth on FPGA with ESP32
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|
0
|
354
|
April 26, 2022
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FPGA as USB Device
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0
|
355
|
April 12, 2022
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Double tap with accelerometer
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0
|
209
|
March 1, 2022
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Interactive C++ on the Kria-SoM in Jupyter Lab
|
|
2
|
1494
|
February 21, 2022
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Tutorial PYNQ: microblaze
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|
0
|
553
|
February 1, 2022
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Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)
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1
|
6539
|
February 4, 2022
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Pynq 2.6 custom board image build method that works
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4
|
2892
|
January 21, 2022
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Cloning a git repository into your board connected to computer
|
|
1
|
667
|
December 13, 2021
|
Developing Verilog AXI Stream Overlays and interfacing to ZYNQ
|
|
13
|
3140
|
December 7, 2021
|
My learning path with Pynq and Zynq
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|
0
|
430
|
November 19, 2021
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Tutorial: use Axi Timer as an IP (no microblaze)
|
|
0
|
422
|
November 16, 2021
|
Tutorial: Creating a hardware design for PYNQ
|
|
9
|
21159
|
November 16, 2021
|
Static IP adress Configuration Issue
|
|
2
|
670
|
November 15, 2021
|
Which Ebook Is Best for Python?
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4
|
566
|
September 24, 2021
|
Which Python Framework is best?
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0
|
348
|
September 14, 2021
|
Common PL Devices on PYNQ
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|
1
|
494
|
July 27, 2021
|
Using ILA to debug IP
|
|
1
|
1459
|
July 22, 2021
|
Tutorial: Rebuild Overlay Tutorial using Vitis_hls and Vivado 2020.2 on ZCU104
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|
1
|
529
|
June 30, 2021
|
16x2 LCD Keypad shield
|
|
2
|
554
|
June 19, 2021
|