PYNQ: PYTHON PRODUCTIVITY

Developing Verilog AXI Stream Overlays and interfacing to ZYNQ

UPDATE 7 Dec 2021:

I’ve broken out this tutorial into two separate tutorials:

Please feel free to access those and comment. They include sources and automation so I should be able to respond to issues and updates much faster.

These tutorials are meant to demonstrate how to use the ZYNQ 7000 and AXI Streaming interface to stream data to and from external peripherals built in the FPGA PL.

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Roger –

Thanks for the simple example. One suggestion:

It appears that the master reset does not reset the read_pointer or tx_done. If I run TestStreamMaster twice, the notebook stops generating output. This can be fixed by adding the masterResetStream to the reset logic for those signals:

  if(!M_AXIS_ARESETN || masterResetStream)                                                            
    begin                                                                        
      read_pointer <= 0;                                                         
      tx_done <= 1'b0;                                                           
    end 

Thanks,

James

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Thanks James- I had missed listing that one edit. It looks like I can’t go back and fix but I appreciate you flagging it (and for going through the tutorial).

Where are the “previous tutorials”?

Hi-

and

Are the prior two tutorials I had written.

Roger

2 Likes

Hi, I really enjoyed your tutorial and it gave me a lot of hints! Do you have a repo that contains the complete code? It seems that some parts in the testbench is missing. Also when I tried to run tutorial on the board the dma has some run time issue. I spent some time in it and couldn’t get it to work.

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Hi @David_Qin,

There’s a two part tutorial where Cathal covers DMA in great detail Tutorial: PYNQ DMA (Part 1: Hardware design)

Mario

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Thank you!

It is not the same thing. Cathal’s tutorial is very good for an absolute beginner but it is very basic. It just tells you how to connect an AXI Stream IP to the processing system. This tutorial rather explains how to use Vivado’s AXI Stream IP template to build an AXI Stream IP but it has some issues and I personally couldn’t reproduce it. It also appears that Roger has only partly provided his code. For instance, he didn’t provide the system Verilog header files for his testbench.

I don’t think anyone can reproduce this tutorial in its current shape. It would be great if it is removed by the admin so that people’s time is not wasted!

2 Likes

Hi Folks- Sorry for the delay in responding. I’ll look into this this coming week and either delete the tutorial and point people to the better one or update mine with the source code.

Hi David- Here is the source code- I’ll rerun this weekend to make sure everything’s still good with the latest Vivado.

https://rogerpease.com/public/PYNQ/AXIMasterSlaveStream/

Roger

Hi Folks- Unfortunately I can’t edit/update or delete this tutorial once it’s been replied to. I’m guessing some things have changed with the new Vivado version. I’ve put in a flag to request it be deleted and I will rebuild it once I get my new board (my TUL-2 board apparently has died on me :frowning: ) along with a git repo so folks can see the complete solution.

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Hi Folks- I put the code on:

rogerpease/AXIMasterSlaveStream: Repo for AXIMasterSlaveStream Tutorial (github.com)

The testbench compiles runs and passes (with an older Vivado) but I’VE NOT HAD A CHANCE TO RE-TEST THE IMAGE! Will do that when I get back from vacation. :slight_smile:

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Hi Folks- I’ve decided to rebuild these tutorials.

These github repos include test source and automation to build the necessary files along with test scripts.

3 Likes