I am trying to pass an array of numbers to the DMA and then add a number to each of them in the PL and then pass it back to the PS, however, I am getting a DMA channel not idle error, when I have put implemented logic for TLAST, TKEEP, TVALID and TREADY:
module adder#(parameter DATA_WIDTH=32, CAPACITY = 10)(
// common signals
input axi_clk,
input axi_reset_n, // active low - as required by AXI protocol
// AXI4-S slave interface
input s_axis_valid,
input [DATA_WIDTH-1:0] s_axis_data,
output s_axis_ready,
// AXI4-S master interface
output reg m_axis_valid,
output reg [DATA_WIDTH-1:0] m_axis_data,
input m_axis_ready,
output reg m_axis_t_last,
output reg [3:0] m_axis_t_keep
);
reg [$clog2(CAPACITY):0] count;
// when are we ready to accept data?
// we are only streaming, so this slave is only ready if the master is ready
assign s_axis_ready = m_axis_ready;
always@(posedge axi_clk)
begin
if(count < CAPACITY)
begin
m_axis_t_last <= 0;
end
else
begin
m_axis_t_last <= 1;
end
end
always@(posedge axi_clk)
begin
if(s_axis_valid & s_axis_ready)
begin
m_axis_data <= m_axis_data + 32'b10100;
count <= count + 1;
end
end
always@(posedge axi_clk)
begin
m_axis_valid <= s_axis_valid & s_axis_ready;// valid data as output when we have valid data in input and already processed it - will come one clk after receiving the input valida data
m_axis_t_keep <= 4'b1111;
end
endmodule
For context, this is my block diagram:
And this is my notebook:
I get this error having ran the cells multiple times, and I did get inconsistent outputs, albeit the outputs of one of the 10 numbers increased by 20 or 40 - still not all correct as I expect an array of 21s in the end - although I did initially pass an array of 1000 0s, so it could be that this is still being read or something - not too sure.