When i export hardware, Vivado produces two HWH files
One for the design
One for subsystem csi2_rx_ss IP in the design
I am providing the HWH file for the design and placing the subsystem hwh in same area.The register definition for csi2_rx_ss IP are not being picked as when i type
ol.csi2.register_map
I get a message “AttributeError: register_map only available if the .hwh is provided”
I was wondering if anyone has been able to work around this issue.
I am able to program registers using
csi2.write() and csi2.read() are working
Will you be willing to post the two .hwh files (and possibly the bitfile - provided you also tell us for which board it is)?
Personally, I’ve never seen this scenario, and I think it is not directly supported in PYNQ.
But, if we can take a look, perhaps we might be able to provide a resolution
Did this ever get resolved? I’m going to work around it by using the mmio directly on a nested axis stream switch as I’m seeing the same thing now in this design. I don’t mind posting the files (they aren’t in git as the the bitstream is 30+ MB.)
Hierarchical HWH is not supported in PYNQ.
I am able to program the registers without issues. It is only that register map for sub hierarchy is not
available and u have to use direct register read and write
