I am new in FPGA world and learning Pynq, vivado, vivado hls and such these time.
I have a problem though, when I was using VC707 to running my acceleration IP using FIFO to process regular expression from file to PS-PL via PCIE with xillybus is successfully working using driver to perform stream file from PS to PL.
However, when I have to use Pynq Z1 to perform such FIFO application with AXI Stream and DMA. I have no idea how to read file text as stream to be processed in PL.
Would you mind to help me?