I am new in FPGA world and learning Pynq, vivado, vivado hls and such these time.
I have a problem though, when I was using VC707 to running my acceleration IP using FIFO to process regular expression from file to PS-PL via PCIE with xillybus is successfully working using driver to perform stream file from PS to PL.
However, when I have to use Pynq Z1 to perform such FIFO application with AXI Stream and DMA. I have no idea how to read file text as stream to be processed in PL.
I guess you can read text file as a numpy array. There are many references on the internet so I guess you can google them.
The xlnk.cma_array has the same type of API as numpy array so you can read files into it directly. Then use DMA to send it over to the streaming interface.
Dear @rock, I tried to learn resize workflow, from IP making using vivado_hls, making tcl, hwh and bitstream from vivado, then running jupyter notebook for both PS and PL.
However, when I tried to make project IP from resize IP, I have encountered some errors.
/ip/hls/resize$ make && make clean
vivado_hls -f script.tcl
****** Vivado™ HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit)
**** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
**** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source /opt/Xilinx/Vivado/2019.2/scripts/vivado_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running ‘/opt/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/vivado_hls’
INFO: [HLS 200-10] For user ‘radhen’ on host ‘radhen’ (Linux_x86_64 version 5.3.0-62-generic) on Wed Jul 08 12:21:09 JST 2020
INFO: [HLS 200-10] On os Ubuntu 18.04.4 LTS
INFO: [HLS 200-10] In directory ‘/home/radhen/Pynq-HelloWorld/boards/ip/hls/resize’
Sourcing Tcl script ‘script.tcl’
INFO: [HLS 200-10] Creating and opening project ‘/home/radhen/Pynq-HelloWorld/boards/ip/hls/resize/resize’.
WARNING: [HLS 200-40] Cannot find design file ‘…/vitis_lib/vision/L2/examples/resize/xf_resize_config.h’
WARNING: [HLS 200-40] Cannot find design file ‘…/vitis_lib/vision/L2/tests/resize/resize_DOWN_BILINEAR_NO_RGB/xf_config_params.h’
INFO: [HLS 200-10] Adding design file ‘xf_axis_config.h’ to the project
INFO: [HLS 200-10] Adding design file ‘xf_resize_accel.cpp’ to the project
INFO: [HLS 200-10] Adding test bench file ‘xf_resize_tb.cpp’ to the project
INFO: [HLS 200-10] Creating and opening solution ‘/home/hendarmawan/Pynq-HelloWorld/boards/ip/hls/resize/resize/solution1’.
INFO: [HLS 200-10] Setting target device to ‘xc7z020-clg484-2’
INFO: [SYN 201-201] Setting up clock ‘default’ with a period of 10ns.
INFO: [SYN 201-201] Setting up clock ‘default’ with an uncertainty of 2.7ns.
INFO: [SCHED 204-61] Option ‘relax_ii_for_timing’ is enabled, will increase II to preserve clock frequency constraints.
WARNING: [HLS 200-40] Cannot find source file …/vitis_lib/vision/L2/tests/resize/resize_DOWN_BILINEAR_NO_RGB/xf_config_params.h; skipping it.
WARNING: [HLS 200-40] Cannot find source file …/vitis_lib/vision/L2/examples/resize/xf_resize_config.h; skipping it.
INFO: [HLS 200-10] Analyzing design file ‘xf_resize_accel.cpp’ …
WARNING: [HLS 200-40] In file included from xf_resize_accel.cpp:30:
./xf_axis_config.h:37:10: fatal error: ‘common/xf_common.hpp’ file not found #include “common/xf_common.hpp”
^
1 error generated.
C preprocessor failed.
while executing
“source script.tcl”
(“uplevel” body line 1)
invoked from within
"uplevel #0 [list source $arg] "
The warning / error WARNING: [HLS 200-40] Cannot find design file ‘…/vitis_lib/vision/L2/tests/resize/resize_DOWN_BILINEAR_NO_RGB/xf_config_params.h’ suggests that file is not present. Maybe you forgot to git clone recursively? You can do git submodule init && git submodule update in your repo to get those files.
