PYNQ DMA Status Flag Error with Custom AXIS Module

I designed a module that uses AXIS protocol to receive, process, and send data with AXIS protocol. My program is:

1- Write a data in memory
2- Receive that data via AXI_DMA receive channel
3- Multiply all data by 2
4- Send it back to memory via AXI_DMA send channel

And my problem is when I use the original M_AXIS and S_AXIS file generated by Vivado all things work well and when I check the DMA status flags they’re all OK but when I use my own module the status flags are like this:

>>> dma_recv.error
>>> dma_recv.idle
>>> dma_recv.running

I get the data complete and well processed but the DMA flags are not right.
What could I do about it. Is there any method for DMA or any status register that I could read the error message or code in it to see why is that error happening?

Block Design:

DMA Config:

Python Notebook:
main.ipynb (6.9 KB)

My custom module AXIS signals:

    // AXI4 Stream (AXIS) Slave
    input s_valid,
    output s_ready,
    input [DATA_WIDTH-1:0] s_data,
    input s_last,

    // AXI4 Stream (AXIS) Master
    output m_valid,
    input m_ready,
    output [DATA_WIDTH-1:0] m_data,
    output m_last,

Vivado v2023.2 (64-bit) SW Build: 4029153 on Fri Oct 13 20:14:34 MDT 2023 IP Build: 4028589 on Sat Oct 14 00:45:43 MDT 2023 SharedData Build: 4025554 on Tue Oct 10 17:18:54 MDT 2023

Board: PYNQ-Z2

Hi @Ali_Shayanpoor,

I wrote an extensive piece with common issues with the DMA.

First of all, I will suggest you simulate your IP and make sure the AXI4-Stream protocol is properly handled. An alternative, would be to add an ILA as mentioned in the blog I shared above.

Please, note that the official Vivado version supported in PYNQ 3.0.1 is 2022.1.