I’m learning how to work with the XADC in the PYNQ framework. I found that the register_map property doesn’t work for the XADC wizard IP, showing the following error:
---------------------------------------------------------------------------
AttributeError Traceback (most recent call last)
<ipython-input-4-12fc6efc3a2a> in <module>
----> 1 xadc.register_map
/usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/overlay.py in register_map(self)
741 self._registers)(self.mmio.array)
742 else:
--> 743 raise AttributeError(
744 "register_map only available if the .hwh is provided")
745 return self._register_map
AttributeError: register_map only available if the .hwh is provided
Is there a reason for this? I would like to handle its EOC signal as an interrupt signal for the PS, following this tutorial, where the register_map property is used to identify the IO ports of the IP.
I’ve tested it in the PYNQ Z2 board for both 2.6 and 2.7 PYNQ versions. As reference, the bitstream and .hwh files (without the interrupt part for simplicity) are attached here, whose block design is below. Also, the minimal code to test it is in the Jupyter nb.
Thanks for providing the .hwh/.bit and a minimal test, this is really useful!
I had a look through the hwh file and I can see that the xadc_wiz_0 module is there. I can also see that it has the s_axi_lite ports and bus interface are there, however, all the register information is missing.
I suspect that maybe this information is not being included in the metadata for some reason. Can you talk us through how you built the bitstream? i.e. what version of the tools were you using?
Have you also tried connecting up Vp_Vn and seeing if the registers appear then?
I’m using Vivado 2019.2. I’ve just created the block design of the picture, running block automations (DDR, FIFO connections for the ZYNQ PS and AXILite connection through the AXI inteconnect block and the reset management). Also, the XADC block has the following configuration differing from the defaults.
I have managed to recreate your problem with a handful of the newer versions of the tools. Unfortunately, I think this may be a bug with Vivado where it does not export the register map for this particular IP correctly.
I’m going to provide you with a workaround shortly that you can try if you’d like, it may work, but it has not been tested extensively. The workaround will be a script that you can run on an XSA generated by the Vivado project; it will grab the missing metadata from the IP repository and inject it into the metadata. You’ll have to use a separate branch of pynq from my fork in the meantime. I’ll also add an issue to PYNQ, and we’ll try and get a solution to this issue by the next release.
Sorry about this; hopefully, we’ll be able to work around the issue in the short term.
I’m afraid that, unfortunately, our new alternative flow to grab the metadata from the IP Catalog was not successful for this either. So it looks like the only way to get the regmap for this particular IP core is to either extract it from the datasheet or to somehow parse it out from a .ttcl file in the IP repository (which our tool is not currently capable of).
Sorry that this didn’t work out. For now, it looks like you’ll have to manually get the regmap yourself from the datasheet and use pynq.MMIO to interact with it.
Thanks for your help! Don’t worry, I started exploring the XADC interaction through MMIO once I saw regmap didn’t work. If I came up with something handy to do this, I will share it here for other PYNQ users.
