Hello team
I’m working with a custom RFSoC design in Vivado and running it on PYNQ. I’ve integrated several spectrum analyser IP blocks in the receive chain.
Board: ZU48DR RFSOC
PYNQ version: PYNQ 3.1
Vivado version: 2024.1
Custom IPs: SpectrumAnalyser (xilinx.com:ip:SpectrumAnalyser:1.1)
Connections include:
radio_vout10_1, radio_vout20_0, radio_vout22_0, radio_vout12_1
vin1_01_0, vin1_23_0, vin2_01_0, vin2_23_0
Clock sources: adc1_clk_0, dac2_clk_0, clk_wiz_307_2M
Reset: proc_sys_reset_0, proc_sys_reset_307_2M
AXI infra: ps8_axi_periph, axi_interconnect_sam_M00_AXI, axi_data_fifo, axi_data_fifo1
RFDC core and Zynq PS (zynq_ultra_ps_e)
Above attached is the custom design, which i am using to validate the spectrum analyser
also attached a hwh file for ur reference
Based on the above provided design, can anyone let me know how can i validate the spectrum analyser through python code
rfsoc_sam.hwh (1.0 MB)
Regards,
Ashritha S