Yes, as @ggillett says, you need to do this yourself. AXI stream protocol has a handshake, so you need to decide how you want to manage this. You may be able to do something really simple like connect your data to the AXI stream data, if your “start” signal acts like a valid, you could add some logic for the handshake/valid.
There are some good tutorials on the internet. E.g. AXI stream:
This is for an AXI slave, and is a little dated, but may still be of use:
The DMA only supports the widths mentioned in the error. You could expand your signal using a “concat” block and concatenate zeros.
You would ignore the upper bits.
There will some inefficiency, but may be good enough for your use case.
In the tutorial you strongly advise not to allow unaligned transfers because that this is not supported by PYNQ v2.6.
However the code of the dma library in PYNQ seems to handle the case where the dre is enabled.
Could you just give me a bit more detailed explanation about this statement ?
I’m currently using PYNQ 2.7 but it seems that the PYNQ dma library code did not change that much.