Tutorial: PYNQ DMA (Part 1: Hardware design)

Yes, as @ggillett says, you need to do this yourself. AXI stream protocol has a handshake, so you need to decide how you want to manage this. You may be able to do something really simple like connect your data to the AXI stream data, if your “start” signal acts like a valid, you could add some logic for the handshake/valid.

There are some good tutorials on the internet. E.g. AXI stream:

This is for an AXI slave, and is a little dated, but may still be of use:



I will take a look. Thank you so much!

When I try to validate the design, I am getting the following error:

I managed to make an AXI stream interface for my IP, however when I try to connect it using a 256 bit DMA interface I am getting this error.

This is how my block design is connected:

The DMA only supports the widths mentioned in the error. You could expand your signal using a “concat” block and concatenate zeros.
You would ignore the upper bits.
There will some inefficiency, but may be good enough for your use case.


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How did you figure this issue out? I’m getting the same error.

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