Yes, as @ggillett says, you need to do this yourself. AXI stream protocol has a handshake, so you need to decide how you want to manage this. You may be able to do something really simple like connect your data to the AXI stream data, if your “start” signal acts like a valid, you could add some logic for the handshake/valid.
There are some good tutorials on the internet. E.g. AXI stream:
This is for an AXI slave, and is a little dated, but may still be of use:
Cathal
I will take a look. Thank you so much!
I managed to make an AXI stream interface for my IP, however when I try to connect it using a 256 bit DMA interface I am getting this error.
This is how my block design is connected:
The DMA only supports the widths mentioned in the error. You could expand your signal using a “concat” block and concatenate zeros.
You would ignore the upper bits.
There will some inefficiency, but may be good enough for your use case.
Regards,
Cathal
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How did you figure this issue out? I’m getting the same error.
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Hi Cathal,
In the tutorial you strongly advise not to allow unaligned transfers because that this is not supported by PYNQ v2.6.
However the code of the dma library in PYNQ seems to handle the case where the dre is enabled.
Could you just give me a bit more detailed explanation about this statement ?
I’m currently using PYNQ 2.7 but it seems that the PYNQ dma library code did not change that much.
Thank you in advance,
Jean-Michel
This is such a really great tutorial! I had some doubts when using the KR 260 to connect to the DMA. As shown in the screenshot, I set the Stream Data Width of all the DMA modules to 32. How can I set the Data Width of the PS part AIX interface?
For the Master axi interface on PS, it needs to connect three s_axi (from DMA 0, DMA 1 and IP) for control. The Slave axi interface on the PS is similar (it connects to MM2S for DMA 0, S2MM and MM2S for DMA 1
Should the AXI on the PS also be set to a 32-bit Data Width in this case? Or should it be set to 128? I am a little confused about the concept of Data Width matching due to the AXI Interconnect module.
Hi, i get the following critical warning when trying to validate the design:
[BD 41-1356] Slave segment </processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM> is not assigned into address space </dma/Data_S2MM>. Please use Address Editor to either assign or exclude it.
Should i be concerned. I am also using Vivado 2024.2 - the results from running connection automation are not the same as in the tutorial:
Hi @rgbblue,
Should i be concerned
Yes, you will not be able to use MMIO. The warning has advise on how to solve this. Please use Address Editor to either assign or exclude it.
Vivado 2024.2 is not tested neither verified by the PYNQ team. We suggest you use Vivado 2022.1.
Mario
