Understanding the interconnect logic of given base overlay

[yefj]

Hello,In official base overlay for RFsoc4x2 there are two interconnect IP’s .If we look at the axi_hpm0_Ipd we have on one side M01_AXI which is connected to GPIO from the right and
M01_ACLK and M01_ARESETN to the left also connected to periphery.
So why the zynq ultrascale+MPSOC is not involve anywhere?
interconnect is supposed to connect between master and slave and we dont see it here at all.
Where is the master?
full overlay PDF is attached.
base.pdf (346.9 KB)

Thanks.

[marioruiz]

Hi @yefj,

What do you mean by this?

So why the zynq ultrascale+MPSOC is not involve anywhere?

These interconnects are connected to the PS.

[marioruiz]

@yefj

interconnect is supposed to connect between master and slave and we dont see it here at all.
Where is the master?

interconnect is supposed to connect between master and slave and we dont see it here at all.
Where is the master?

Do you mean to the PS? Master and Slaves have different functionality in the PS. The Master initiates the transactions, whereas the salve responds/accepts the transactions.