You don’t need the AXI FIFO. This is used in the example to loopback from one DMA write channel → read channel.
You should replace this with your IP.
The source code for the example in the tutorial is here:
https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/blob/2021.2/Interface/Streaming/using_axi_stream_with_side_channel_data/example.cpp
Use this as a template for your application.
It shows how to manage TLAST. If you do not set TLAST it will be removed.
TDATA_NUM_BYTES does not match …
You have a data width mismatch between your IP and the DMA. It looks like you set the DMA width to 32 bits but the output from your IP is 16 bits. You can change the width of the DMA, or use an AXI interconnect to convert from 16-bit to 32-bit. Changing the width in the DMA is simpler.
You can find the settings for this in the “DMA read and write channels” in the DMA tutorial
Cathal