Currently i only have experience doing it in HLS, in these 3 videos you can learn how to use it using HLS.
It’s fairly straightforward.
There is also a possibility to define AXI IPs using vivado but I don’t know how yet.
To get quick results, it’s probably best to write a bridging IP in HLS to handle communication with the AXI bus, and connect it to your VHDL/verilog modules. It’s stupid but it will work, I think.
Best of luck