How could we use a axi interface in pynq?

[RogerPease]

If you want to do this in Verilog I did a few tutorials on this in the Learn area:

Tutorial: Creating a new Verilog Module Overlay

This is a tutorial targeted at Verilog and Python users who wish to use Zynq 7000 to do Verilog FPGA module development and interface their Verilog in the PL to the PS system. I went through this learning curve a few months ago and wanted to share my experience to “pay it forward”. I used a TUL-2 Board. Design Steps and decisions The general flow of design steps I followed are: Develop the IP. You will interface to your IP through a memory mapped interface. Instance the IP in an AXI IP Wrapp…

Tutorial: Creating a Verilog Overlay with Bidirectional Pins

Building a Verilog overlay with Bidirectional pins Background This tutorial is targeted at users who wish to interface the PL of a Zynq 7000 and use pins as inputs, outputs or Bidirectional pins. This tutorial was developed on a TUL-2 Board… Other development boards may require modifications. Sample sources are linked. Use caution when selecting pins or applying drive values to pins as contending drivers (either from your board or you) can damage the part or the board. Also be sure to select pin…