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PYNQ-Z1 pinout
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2
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379
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March 4, 2025
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PYNQ ZU pinout diagram
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2
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30
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March 4, 2025
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RFSoC 4x2 PLL Lock Leds don't turn on
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2
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71
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March 4, 2025
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PYNQ Z1 - max. PL PLL frequency?
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1
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32
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March 4, 2025
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What is constrain pin of the clock present on pynq-Zu board
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1
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18
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March 4, 2025
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Add an SDIO wifi kernel module while builing a new PYNQ image
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0
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25
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March 4, 2025
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Writing an image to an IP using AXI4 Master
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8
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195
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March 4, 2025
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Addressing PMODs in MicroZed boards running a PYNQ image
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4
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45
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March 2, 2025
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Axi dma peformance with different frequencies
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1
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120
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March 1, 2025
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RFSoC 4x2 OFDM channel estimation
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2
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76
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February 28, 2025
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CacheMetadataError ZCU102 PYNQ3.0.1 Vivado2022.1
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2
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27
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February 28, 2025
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PYNQ is available for Avnet Microzed SOM
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1
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512
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February 27, 2025
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Custom fs in mts overlay
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3
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39
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February 26, 2025
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My DMA send and receive keep stalling if i send multipple data
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3
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64
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February 26, 2025
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Want to implement bilateral filter in pynq z2
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0
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16
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February 25, 2025
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ADC input on Pynq-ZU
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1
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35
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February 24, 2025
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Pynq-Z2 mechanical dimensions
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2
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55
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February 22, 2025
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Composable Pipeline for ZCU104
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1
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453
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February 21, 2025
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Pulse generator using transceivers with Pynq
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0
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55
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February 19, 2025
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RFDC Start Up Fail - ADC 0 timed out at state 7 in XRFdc_WaitForRestartClr
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6
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422
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February 19, 2025
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AXI GPIO connection with my 4 bit counter
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3
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84
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February 19, 2025
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Pynq zu sysmon adc read
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0
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15
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February 18, 2025
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Adding btusb kernel module to PYNQ OS
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1
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271
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February 18, 2025
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Sudo modprobe btusb error
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0
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46
|
February 18, 2025
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AXI Data FiFo not detect by PYNQ
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2
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12
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February 17, 2025
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Use AXI lite interface for setting parameter HLS IP
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5
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1119
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February 17, 2025
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SYSMON IP configuration
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0
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14
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February 17, 2025
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Designing an Overlay using Vivado Integrated Logic Analyzer (ILA) [Part 1]
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10
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708
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February 14, 2025
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Allocate fails with error
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8
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130
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February 12, 2025
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Setting up PYNQ-ZU on Vivado 2020.1 for hls4ml
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1
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90
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February 14, 2025
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