PYNQ: PYTHON PRODUCTIVITY FOR ZYNQ

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Topic Replies Activity
PL FCLK0 changes as soon as overlay loads bitfile 6 January 13, 2020
Overlay Instantiation 2 January 10, 2020
Build with v2.5 on Ubuntu 16.04 16 January 9, 2020
Readframe in VDMA 1 January 7, 2020
Looking for pynq_z1_v2.5.img file viewer application soft 2 January 7, 2020
How to send data from AXI-LITE port to PL and receive data from AXI DMA 3 January 7, 2020
Pynq-z1 board does not power up 2 January 6, 2020
Sobel filter design 2 January 6, 2020
The difference of two bitstreams in PYNQ build environment 2 January 6, 2020
Using PL DDR4 MIG IP 2 January 6, 2020
Help need to build for this board (DSDB NI Elvis III) 4 January 6, 2020
Taking over control of displayport output using live feed settings 1 January 5, 2020
PYNQ-Z2 can't boot "DRAM:ECC disabled 512 MiB" 3 January 4, 2020
PYNQ-Z2 with libgpiod - what's that on line 62? 2 January 3, 2020
Efficient PS<->PL GPIO 3 January 2, 2020
ValueError: Could not find UIO device for interrupt pin for IRQ number 0 5 January 2, 2020
Regaeding arduino 1 December 29, 2019
How to create an IP that get HDMI frames as parameters? 1 December 28, 2019
Coresight Access Library with Pynq Z1 1 December 26, 2019
Re-build linux-xlnx , u-boot for Pynq Z1 5 December 26, 2019
Encrypted bitstream 1 December 23, 2019
Spark application on PYNQ 7 December 23, 2019
What to edit sources.list with to install packages? 1 December 23, 2019
Using AXI DMA on ZCU104 7 December 21, 2019
AXI BRAM breaks overlay design 4 December 20, 2019
PYNQ 2.5.1 custom board building mixed with pynq boards 2 December 20, 2019
Guidance on using VDMA interrupt 3 December 19, 2019
How to set the HDMI in/out resolution? 2 December 19, 2019
Adding IP to a PYNQ overlay - tutorial problem 3 December 19, 2019
More than one application on board 3 December 18, 2019