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Vitis debugger doesn't find microblaze v core
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1
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6
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July 16, 2024
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How to implement my own UART transceiver on PYNQ Z1
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0
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9
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July 16, 2024
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Can't write bitstream to ZCU216 using qpsk_overlay()
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3
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100
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July 15, 2024
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Connecting UART to PL
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6
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15
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July 15, 2024
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How to connect ethernet port to PL
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3
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29
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July 15, 2024
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Connecting RFSoC to a MacOS computer
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15
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26
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July 15, 2024
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Error loading overlay: RuntimeError: Programming Device failed: ENODEV (19) No such device
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2
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211
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July 13, 2024
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Pynq Throwing Boost Exception, /dev/dri/by-path/is missing
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5
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799
|
July 13, 2024
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I am having an issue with partial reconfiguration
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5
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16
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July 13, 2024
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Error loading bitstream - PYNQ v3.0.1. Zybo-010
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4
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833
|
July 12, 2024
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MIPI + Resizing HLS IP Integration Issue
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6
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41
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July 10, 2024
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Vitis support
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1
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27
|
July 9, 2024
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Access Acceleration kernel without DMA
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7
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898
|
July 9, 2024
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Problem with the image for pynq in the z-turnboard v2
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6
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21
|
July 9, 2024
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Error then building PYNQ for microzed board
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4
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31
|
July 8, 2024
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ZCU104 v2.5 PYNQ image can NOT be found
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3
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472
|
July 7, 2024
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PYNQ image for custom board make error
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5
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1587
|
July 7, 2024
|
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ValueError: embedded null byte while implementing DPR on ZCU216
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14
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79
|
July 8, 2024
|
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PYNQ for ZCU216 RFSOC board
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6
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2299
|
July 5, 2024
|
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Building PYNQ 2.5 and 2.6 for UltraZed on the IOCC
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2
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650
|
July 5, 2024
|
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RFSoc 4x2 Signal generation
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2
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64
|
July 4, 2024
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Is it normal for different tiles of an ADC to receive signals with different amplitudes?
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2
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20
|
July 4, 2024
|
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Time library needs to be imported over and over again
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3
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24
|
July 4, 2024
|
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Understanding AmplitudeController Class in RFSoC4x2 Xilinx Example
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0
|
26
|
July 4, 2024
|
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Understanding AdcChannel Class in RFSoC4x2 Xilinx Example
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0
|
21
|
July 4, 2024
|
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RFSoC4x2 frequent disconnection
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1
|
25
|
July 3, 2024
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PYNQ Z-2 - v3.0.1 MAC Address
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2
|
278
|
July 3, 2024
|
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Is PYNQ using PCAP interface to configure the FPGA?
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0
|
21
|
July 3, 2024
|
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Using UART peripheral in pynq-z2
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0
|
32
|
July 2, 2024
|
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Base Overlay's DFX AXI Shutdown Managers
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4
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33
|
July 2, 2024
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