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Transmitting x ms frames with dac_player
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5
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65
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October 2, 2024
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Kernel died Issue When Loading TFLite Model on Pynq-Z2 Board
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0
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82
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June 15, 2024
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Pynq z2 fft
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1
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74
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March 25, 2025
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Cannot download latest image of RFSoC 4x2
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3
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47
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May 21, 2024
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Best Vivado/Vitis Version for PYNQ-Z1 with SD Image v3.0.1 or Most Stable Combo?
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4
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50
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April 24, 2025
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Adding Overlay for given bit file is not working 'NoneType' object has no attribute 'split' Error in hwh_parser.py
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0
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80
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May 22, 2024
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Base Overlay's DFX AXI Shutdown Managers
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4
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48
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July 2, 2024
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PYNQ for versal boards
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1
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57
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February 11, 2025
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使用vitis-aiDPU进行部署
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1
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53
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May 28, 2024
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[RFSOC ZCU216]Transmit baseband signal
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0
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79
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June 3, 2024
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Pynq-Z2 mechanical dimensions
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2
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45
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February 22, 2025
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Question about sampling rate of xadc
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2
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48
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January 12, 2025
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How to resolve timing violations in a Vivado design?
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2
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49
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December 11, 2024
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RFSoC 4x2 ADC tile
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3
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45
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April 8, 2025
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PYNQ3.0 build failed - Could not find "pl-delete-nodes-.dtsi"
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3
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47
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October 9, 2024
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Using PYNQ to control RFsoc4*2's dac_block' mixer
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2
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53
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October 29, 2024
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Bit stream loading error PYNQ 2.7
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0
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73
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May 31, 2024
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MMIO with connected to custom HDL can't use the clock
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6
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31
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September 8, 2024
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RFSoC 4x2 Kit
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0
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70
|
August 6, 2024
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RFSoC 4x2 PLL Lock Leds don't turn on
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2
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64
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March 4, 2025
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How to use PYNQ axidma API without overlay
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7
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35
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January 8, 2025
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PYNQ-ZU labs
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1
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53
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November 25, 2024
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I got an error when using the PYNQ-ZU development board for yolov5 reasoning, how do I fix it
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1
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50
|
June 27, 2024
|
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PYNQ Coverage
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2
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47
|
January 23, 2025
|
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Error running pynq with Alveo u200
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3
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42
|
June 29, 2024
|
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Error with Building the Image From Source
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0
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70
|
June 20, 2024
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PYNQ ZU External Analog Input
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6
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39
|
February 16, 2025
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Adc/dac transfer data request
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2
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47
|
September 6, 2024
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DynamicPLLConfig freezes RFSoC4x2
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1
|
50
|
August 6, 2024
|
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About PYNQ support for Arty-Z7 board
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3
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36
|
September 30, 2024
|
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Understanding AdcChannel Class in RFSoC4x2 Xilinx Example
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2
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61
|
August 2, 2024
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ZCU216 basic ADC and DAC IQ send and receive example
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0
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66
|
July 31, 2024
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Unable to acquire full analog pulse from XADC via AXI DMA (limited to 256 samples)
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3
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43
|
April 28, 2025
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RFSoC 4X2 PYNQ, no ip detected
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3
|
47
|
August 28, 2024
|
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Blocks on rfsoc 4*2 board
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3
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48
|
August 9, 2024
|
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PYNQ with interrupt from input pins
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5
|
24
|
April 19, 2025
|
|
PYNQ board connection stops as soon as I load the bitstream through the overlay on Jupyter
|
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5
|
33
|
April 2, 2025
|
|
Trace Analyzer Arduino IOP PYNQ-Z2
|
|
4
|
37
|
May 1, 2025
|
|
Logictools generators fail when run
|
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6
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36
|
February 4, 2025
|
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Is it normal for different tiles of an ADC to receive signals with different amplitudes?
|
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2
|
34
|
July 4, 2024
|
|
The Strathclyde RFSoC Studio Installer for PYNQ RFSoC 4x2
|
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1
|
42
|
September 1, 2024
|
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Time library needs to be imported over and over again
|
|
3
|
29
|
July 4, 2024
|
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Issue Connecting Camera to PYNQ-Z2 Board (Version 3.0.1)
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2
|
34
|
October 29, 2024
|
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Addressing PMODs in MicroZed boards running a PYNQ image
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4
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40
|
March 2, 2025
|
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How to read data from dma for given adress
|
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4
|
26
|
November 15, 2024
|
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Logictools bug fix
|
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3
|
30
|
January 22, 2025
|
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Composable pipeline need to wait before readframe() from VDMA
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6
|
35
|
December 6, 2024
|
|
Kria PYNQ DMA connect problem
|
|
3
|
36
|
March 10, 2025
|
|
Does USB Bluetooth adapters work with pynq Z2 board?
|
|
3
|
33
|
November 28, 2024
|
|
Ask about pynq architecture
|
|
4
|
35
|
November 18, 2024
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